\doxysection{DTS\+\_\+\+Type\+Def Struct Reference}
\hypertarget{struct_d_t_s___type_def}{}\label{struct_d_t_s___type_def}\index{DTS\_TypeDef@{DTS\_TypeDef}}


DTS.  




{\ttfamily \#include $<$stm32h723xx.\+h$>$}

\doxysubsubsection*{Public Attributes}
\begin{DoxyCompactItemize}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_t_s___type_def_a6aebcef8920afb0193765f3fa74a2357}{CFGR1}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_d_t_s___type_def_a2d50d35649b40071297746e34e0f39a8}{RESERVED0}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_t_s___type_def_acc67fcc92683e343783d175c80d4efe2}{T0\+VALR1}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_d_t_s___type_def_a85fa922b9de2c943c7f4fad2531e64a6}{RESERVED1}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_t_s___type_def_a10d3db9e0ed5ba16d2a3eb90cc265a61}{RAMPVALR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_t_s___type_def_a2a2bfabbe5bbb5514c12ef765b35ec8f}{ITR1}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_d_t_s___type_def_a5fe1e7ed92e68637b779399122461591}{RESERVED2}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_t_s___type_def_a158861b2eb2b0e479fc835542f6bd06c}{DR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_t_s___type_def_a394860e24d1f493911e31943e6d22c64}{SR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_t_s___type_def_a022e6747adc4e3714ff66ffdc46a9cb2}{ITENR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_t_s___type_def_a9201aabd9926db6d5bc266bf3e0347a6}{ICIFR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_t_s___type_def_abed6d50969874f34b1ef2b87fa9f839c}{OR}}
\end{DoxyCompactItemize}


\doxysubsection{Detailed Description}
DTS. 

\label{doc-variable-members}
\Hypertarget{struct_d_t_s___type_def_doc-variable-members}
\doxysubsection{Member Data Documentation}
\Hypertarget{struct_d_t_s___type_def_a6aebcef8920afb0193765f3fa74a2357}\index{DTS\_TypeDef@{DTS\_TypeDef}!CFGR1@{CFGR1}}
\index{CFGR1@{CFGR1}!DTS\_TypeDef@{DTS\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CFGR1}{CFGR1}}
{\footnotesize\ttfamily \label{struct_d_t_s___type_def_a6aebcef8920afb0193765f3fa74a2357} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DTS\+\_\+\+Type\+Def\+::\+CFGR1}

DTS configuration register, Address offset\+: 0x00 \Hypertarget{struct_d_t_s___type_def_a158861b2eb2b0e479fc835542f6bd06c}\index{DTS\_TypeDef@{DTS\_TypeDef}!DR@{DR}}
\index{DR@{DR}!DTS\_TypeDef@{DTS\_TypeDef}}
\doxysubsubsection{\texorpdfstring{DR}{DR}}
{\footnotesize\ttfamily \label{struct_d_t_s___type_def_a158861b2eb2b0e479fc835542f6bd06c} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DTS\+\_\+\+Type\+Def\+::\+DR}

DTS data register, Address offset\+: 0x1C \Hypertarget{struct_d_t_s___type_def_a9201aabd9926db6d5bc266bf3e0347a6}\index{DTS\_TypeDef@{DTS\_TypeDef}!ICIFR@{ICIFR}}
\index{ICIFR@{ICIFR}!DTS\_TypeDef@{DTS\_TypeDef}}
\doxysubsubsection{\texorpdfstring{ICIFR}{ICIFR}}
{\footnotesize\ttfamily \label{struct_d_t_s___type_def_a9201aabd9926db6d5bc266bf3e0347a6} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DTS\+\_\+\+Type\+Def\+::\+ICIFR}

DTS Clear Interrupt flag register, Address offset\+: 0x28 \Hypertarget{struct_d_t_s___type_def_a022e6747adc4e3714ff66ffdc46a9cb2}\index{DTS\_TypeDef@{DTS\_TypeDef}!ITENR@{ITENR}}
\index{ITENR@{ITENR}!DTS\_TypeDef@{DTS\_TypeDef}}
\doxysubsubsection{\texorpdfstring{ITENR}{ITENR}}
{\footnotesize\ttfamily \label{struct_d_t_s___type_def_a022e6747adc4e3714ff66ffdc46a9cb2} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DTS\+\_\+\+Type\+Def\+::\+ITENR}

DTS Interrupt enable register, Address offset\+: 0x24 \Hypertarget{struct_d_t_s___type_def_a2a2bfabbe5bbb5514c12ef765b35ec8f}\index{DTS\_TypeDef@{DTS\_TypeDef}!ITR1@{ITR1}}
\index{ITR1@{ITR1}!DTS\_TypeDef@{DTS\_TypeDef}}
\doxysubsubsection{\texorpdfstring{ITR1}{ITR1}}
{\footnotesize\ttfamily \label{struct_d_t_s___type_def_a2a2bfabbe5bbb5514c12ef765b35ec8f} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DTS\+\_\+\+Type\+Def\+::\+ITR1}

DTS Interrupt threshold register, Address offset\+: 0x14 \Hypertarget{struct_d_t_s___type_def_abed6d50969874f34b1ef2b87fa9f839c}\index{DTS\_TypeDef@{DTS\_TypeDef}!OR@{OR}}
\index{OR@{OR}!DTS\_TypeDef@{DTS\_TypeDef}}
\doxysubsubsection{\texorpdfstring{OR}{OR}}
{\footnotesize\ttfamily \label{struct_d_t_s___type_def_abed6d50969874f34b1ef2b87fa9f839c} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DTS\+\_\+\+Type\+Def\+::\+OR}

DTS option register 1, Address offset\+: 0x2C \Hypertarget{struct_d_t_s___type_def_a10d3db9e0ed5ba16d2a3eb90cc265a61}\index{DTS\_TypeDef@{DTS\_TypeDef}!RAMPVALR@{RAMPVALR}}
\index{RAMPVALR@{RAMPVALR}!DTS\_TypeDef@{DTS\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RAMPVALR}{RAMPVALR}}
{\footnotesize\ttfamily \label{struct_d_t_s___type_def_a10d3db9e0ed5ba16d2a3eb90cc265a61} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DTS\+\_\+\+Type\+Def\+::\+RAMPVALR}

DTS Ramp value register, Address offset\+: 0x10 \Hypertarget{struct_d_t_s___type_def_a2d50d35649b40071297746e34e0f39a8}\index{DTS\_TypeDef@{DTS\_TypeDef}!RESERVED0@{RESERVED0}}
\index{RESERVED0@{RESERVED0}!DTS\_TypeDef@{DTS\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED0}{RESERVED0}}
{\footnotesize\ttfamily \label{struct_d_t_s___type_def_a2d50d35649b40071297746e34e0f39a8} 
uint32\+\_\+t DTS\+\_\+\+Type\+Def\+::\+RESERVED0}

Reserved, Address offset\+: 0x04 \Hypertarget{struct_d_t_s___type_def_a85fa922b9de2c943c7f4fad2531e64a6}\index{DTS\_TypeDef@{DTS\_TypeDef}!RESERVED1@{RESERVED1}}
\index{RESERVED1@{RESERVED1}!DTS\_TypeDef@{DTS\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED1}{RESERVED1}}
{\footnotesize\ttfamily \label{struct_d_t_s___type_def_a85fa922b9de2c943c7f4fad2531e64a6} 
uint32\+\_\+t DTS\+\_\+\+Type\+Def\+::\+RESERVED1}

Reserved, Address offset\+: 0x0C \Hypertarget{struct_d_t_s___type_def_a5fe1e7ed92e68637b779399122461591}\index{DTS\_TypeDef@{DTS\_TypeDef}!RESERVED2@{RESERVED2}}
\index{RESERVED2@{RESERVED2}!DTS\_TypeDef@{DTS\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED2}{RESERVED2}}
{\footnotesize\ttfamily \label{struct_d_t_s___type_def_a5fe1e7ed92e68637b779399122461591} 
uint32\+\_\+t DTS\+\_\+\+Type\+Def\+::\+RESERVED2}

Reserved, Address offset\+: 0x18 \Hypertarget{struct_d_t_s___type_def_a394860e24d1f493911e31943e6d22c64}\index{DTS\_TypeDef@{DTS\_TypeDef}!SR@{SR}}
\index{SR@{SR}!DTS\_TypeDef@{DTS\_TypeDef}}
\doxysubsubsection{\texorpdfstring{SR}{SR}}
{\footnotesize\ttfamily \label{struct_d_t_s___type_def_a394860e24d1f493911e31943e6d22c64} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DTS\+\_\+\+Type\+Def\+::\+SR}

DTS status register Address offset\+: 0x20 \Hypertarget{struct_d_t_s___type_def_acc67fcc92683e343783d175c80d4efe2}\index{DTS\_TypeDef@{DTS\_TypeDef}!T0VALR1@{T0VALR1}}
\index{T0VALR1@{T0VALR1}!DTS\_TypeDef@{DTS\_TypeDef}}
\doxysubsubsection{\texorpdfstring{T0VALR1}{T0VALR1}}
{\footnotesize\ttfamily \label{struct_d_t_s___type_def_acc67fcc92683e343783d175c80d4efe2} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DTS\+\_\+\+Type\+Def\+::\+T0\+VALR1}

DTS T0 Value register, Address offset\+: 0x08 

The documentation for this struct was generated from the following file\+:\begin{DoxyCompactItemize}
\item 
C\+:/\+Users/\+ASUS/\+Desktop/dm-\/ctrl\+H7-\/balance-\/9025test/\+Drivers/\+CMSIS/\+Device/\+ST/\+STM32\+H7xx/\+Include/\mbox{\hyperlink{stm32h723xx_8h}{stm32h723xx.\+h}}\end{DoxyCompactItemize}
